Register Transfer Level (RTL) design validation is a crucial stage in thehardware design process. We present a new approach to enhancing RTL designvalidation using available software techniques and tools. Our approach convertsthe source code of a RTL design into a C++ software program. Then a powerfulsymbolic execution engine is employed to execute the converted C++ programsymbolically to generate test cases. To better generate efficient test cases,we limit the number of cycles to guide symbolic execution. Moreover, we addbit-level symbolic variable support into the symbolic execution engine.Generated test cases are further evaluated by simulating the RTL design to getaccurate coverage. We have evaluated the approach on a floating point unit(FPU) design. The preliminary results show that our approach can deliverhigh-quality tests to achieve high coverage.
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